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IS62LV12816L IS62LV12816LL
IS62LV12816L IS62LV12816LL
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
FEATURES
High-speed access times: 55, 70, 100 ns CMOS low power operation -- 120 mW (typical) operating -- 6 W (typical) CMOS standby TTL compatible interface levels Single 2.7V-3.6V Vcc power supply Fully static operation: no clock or refresh required Three state outputs Data control for upper and lower bytes Industrial temperature available Available in the 44-pin TSOP-2 and 48-pin 6*8mm TF-BGA
DESCRIPTION The 1+51 IS62LV12816L and IS62LV12816LL are high-speed,
2.097,152-bit static RAMs organized as 131,072 words by 16 bits. They are fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected) or when CE is low and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62LV12816L and IS62LV12816LL are packaged in the JEDEC standare 44-pin 400mil TSOP-2 and 48-pin 6*8mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16 MEMORY ARRAY
VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE OE WE UB LB CONTROL CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
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IS62LV12816L IS62LV12816LL
PIN CONFIGURATIONS
44-Pin TSOP-2
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
48-Pin TF-BGA
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
1 A B C D E F G H
LB I/O8 I/O9 GND Vcc I/O14 I/O15 NC
2
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
3
A0 A3 A5 NC NC A14 A12 A9
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6
N/C I/O0 I/O2 Vcc GND I/O6 I/O7 NC
PIN DESCRIPTIONS
A0-A16 I/O0-I/O15 CE OE WE Address Inputs Data Input/Output Chip Enable Input Output Enable Input Write Enable Input LB UB NC Vcc GND Lower-byte Control (l/O0-I/O7) Upper-byte Control (l/O8-I/O15) No Connection Power Ground
TRUTH TABLE
Mode Not Selected WE CE H L L L L L L L L L OE X X H X L L L X X X LB X H X H L H L L H L UB X H X H H L L H L L I/O0/-I/O7 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O PIN I/O8-I/O15 High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current ISB, ISB ISB, ISB ICC ISB ICC
X X Output Disabled H X Read H H H Write L L L
ICC
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IS62LV12816L IS62LV12816LL
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C 40C to +85C VCC 2.7V - 3.6V 2.7V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TBIAS VCC TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vcc related to GND Storage Temperature Power Dissipation Value 0.5 to Vcc + 0.5 40 to +85 0.3 to +4.0 65 to +150 1.0 Unit V C V C W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage Test Conditions VCC = Min., IOH = 1 mA VCC = Min., IOL = 2.1 mA Min. 2.0 2.2 0.2 1 1 Max. 0.4 VCC + 0.2 0.4 1 1 Unit V V V V A A
GND VIN VCC GND VOUT VCC, OUTPUTS DISABLED
Notes: 1. VIL(min.) = 2.0V for pulse width less than 10 ns.
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters.
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IS62LV12816L IS62LV12816LL
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.3V See Figures 1 and 2
AC TEST LOADS
1 TTL OUTPUT 100 pF Including jig and scope
OUTPUT 5 pF Including jig and scope 1 TTL
Figure 1
Figure 2
IS62LV12816L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC ISB Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) OR ULB Control ISB CMOS Standby Current (CMOS Inputs) OR ULB Control Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL, CE VIH, f = 0 Com. Ind. Com. Ind. -55 Min. Max. 40 45 0.4 1.0 -70 Min. Max. 30 35 0.4 1.0 -100 Min. Max. 20 25 0.4 1.0 Unit mA mA
VCC = Max., VIN = VIH or VIL CE = VIL, f = 0, UB = VIH, LB = VIH VCC = Max., CE VCC 0.2V, VIN VCC 0.2V, or VIN 0.2V, f = 0 Com. Ind. 35 50 35 50 35 50 A
VCC = Max., CE = VIL VIN 0.2V, f = 0, UB / LB = VCC 0.2V
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
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IS62LV12816L IS62LV12816LL
IS62LV12816LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC ISB Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) OR ULB Control ISB CMOS Standby Current (CMOS Inputs) OR ULB Control Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL, CE VIH, f = 0 Com. Ind. Com. Ind. -55 Min. Max. 40 45 0.4 1.0 -70 Min. Max. 30 35 0.4 1.0 -100 Min. Max. 20 25 0.4 1.0 Unit mA mA
VCC = Max., VIN = VIH or VIL CE = VIL, f = 0, UB = VIH, LB = VIH VCC = Max., f = 0 CE VCC 0.2V, VIN VCC 0.2V, or VIN 0.2V, f = 0 Com. Ind. 10 15 10 15 10 15 A
VCC = Max., CE = VIL VIN 0.2V, f = 0, UB / LB = VCC 0.2V
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time
Min. 55 10 5 0 10 0 0
-55
Max. 55 55 30 20 20 55 25
Min. 70 10 5 0 10 0 0
-70
Max. 70 70 35 25 25 70 25
-100 Min. Max. 100 15 5 0 10 0 0 100 100 50 30 30 100 35
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE tDOE tHZOE tLZOE
OE to High-Z Output OE to Low-Z Output
tHZCE CE to High-Z Output tLZCE CE to Low-Z Output tBA tHZB tLZB
LB, UB Access Time LB, UB o High-Z Output LB. UB to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
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IS62LV12816L IS62LV12816LL
AC TEST LOADS READ CYCLE NO.1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
tRC
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS, OE, AND UB/LB Controlled)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE
tLZCE
tLZOE tACE tHZCE
LB, UB
tBA tHZB
DATA VALID
DOUT
HIGH-Z
tLZB
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transitions.
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IS62LV12816L IS62LV12816LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End
!
Min. 55 50 50 0 0 45 45 25 0 5
-55
Max. 30
Min. 70 65 65 0 0 60 60 30 0 5
-70
Max. 30
-100 Min. Max 100 80 80 0 0 80 80 40 0 5 40
Unit ns ns ns ns ns ns ns ns ns ns ns
tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE
WE LOW to High-Z Output
tLZWE! WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW, and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS, Controlled, OE =
HIGH or LOW)
t WC
ADDRESS
VALID ADDRESS
t SA
CS
t SCS
t HA
WE
t AW t PWE1 t PWE2 t PWB
UB, LB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS) [ (LB) = (UB) ] (WE).
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IS62LV12816L IS62LV12816LL
WRITE CYCLE NO. 2 (WE Controlled; OE is HIGH During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CS
LOW
t AW t PWE1
WE
t SA
UB, LB
t PWB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
WRITE CYCLE NO. 3 (WE Controlled; OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE CS
LOW
t HA
LOW
t AW t PWE2
WE
t SA
UB, LB
t PWB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
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IS62LV12816L IS62LV12816LL
WRITE CYCLE NO. 4 (UB / LB Controlled)
t WC
ADDRESS
ADDRESS 1
t WC
ADDRESS 2
OE
t SA
CS
LOW
WE
t HA t SA t PWB t PWB
WORD 2
t HA
UB, LB
WORD 1
t HZWE
DOUT
HIGH-Z
t LZWE t HD
DATAIN VALID
DATA UNDEFINED
t SD
DIN
t SD
DATAIN VALID
t HD
DATA RETENTION SWITCHING CHARACTERISTICS (L/LL)
Symbol Parameter Vcc for Data Retention Data Retention Current Test Condition See Data Retention Waveform Vcc = 2.0V, CE Vcc 0.2V Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) Min. 1.5 0 Max. 3.6 20 5 25 7 Unit V A A A A ns ns
VDR
IDR
tSDR tRDR
Data Retention Setup Time Recovery Time
See Data Retention Waveform See Data Retention Waveform
(CE Controlled)
Data Retention Mode
tRC
DATA RETENTION WAVEFORM
tSDR VCC 2.7V
tRDR
2.2V
VDR CE VCC - 0.2V
CE GND
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IS62LV12816L IS62LV12816LL
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) Order Part No. 55 70 100 IS62LV12816L-55T IS62LV12816L-55B IS62LV12816L-70T IS62LV12816L-70B IS62LV12816L-100T IS62LV12816L-100B Package 400mil TSOP-2 6*8mm TF-BGA 400mil TSOP-2 6*8mm TF-BGA 400mil TSOP-2 6*8mm TF-BGA
Industrial Range: -40C to +85C
Speed (ns) Order Part No. 55 70 100 IS62LV12816L-55TI IS62LV12816L-55BI IS62LV12816L-70TI IS62LV12816L-70BI IS62LV12816L-100TI IS62LV12816L-100BI Package 400mil TSOP-2 6*8mm TF-BGA 400mil TSOP-2 6*8mm TF-BGA 400mil TSOP-2 6*8mm TF-BGA
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) Order Part No. 55 70 100 IS62LV12816LL-55T IS62LV12816LL-55B IS62LV12816LL-70T IS62LV12816LL-70B IS62LV12816LL-100T IS62LV12816LL-100B Package 400mil TSOP-2 6*8mm TF-BGA 400mil TSOP-2 6*8mm TF-BGA 400mil TSOP-2 6*8mm TF-BGA
Industrial Range: -40C to +85C
Speed (ns) Order Part No. 55 70 100 IS62LV12816LL-55TI IS62LV12816LL-55BI IS62LV12816LL-70TI IS62LV12816LL-70BI IS62LV12816LL-100TI IS62LV12816LL-100BI Package 400mil TSOP-2 6*8mm TF-BGA 400mil TSOP-2 6*8mm TF-BGA 400mil TSOP-2 6*8mm TF-BGA
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Integrated Circuit Solution Inc.
BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
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